EPR-15112 information

Notes

Memory:
0x0000-0x7FFF	ROM
0x8000-0xBFFF	Internal RAM [MEM]
0xC000-0xFFFF	Shared RAM [SHARE]

I/O:
0x00-0x1F	DLC	MB89374
0x20-0x2F	DMA	MB89237A
0x40		SYN
0x60		ZFG

DMA:
DMA Channel 0	
DMA Channel 1	
DMA Channel 2	DLC-to-Memory
DMA Channel 3	Memory-to-DLC

Locations:
0x8040-0x8065	DMA-Config CH0,CH1 (copy of 0x00F8..)
0x8070-0x8095	DMA-Config CH0,CH1 (copy of 0x00F8..)
0x80A0-0x80B3	DMA-Config CH2 (copy of 0x0094..)
0x80C0-0x80D3	DMA-Config CH3 (copy of 0x0080..)
0x80E0-0x80F3	DMA-Config CH2 (copy of 0x0094..)
0x8100-0x8113	DMA-Config CH3 (copy of 0x0080..)

Internal:
8000H	VINT related flag		(usualy set to 0, then read until NOT zero)
8001H	VINT related counter	(used by 043BH, 03D4H)

8003H	? (2 on reset)

8005H	? (set to 0)
8006H	slave flag
8007H	relay flag
8008H	total node count - will HALT if 9 or larger.
8009H	local node id
800AH	ring flag? (0 on single, 1 on others)
800BH	Single Byte source 		(Master CH3 DMA source)
800CH	Single Byte destination	(Master CH2 DMA destination)

800EH	? (0 on reset)
800FH	? (lo byte)\
8010H	? (hi byte)-- 0x85CE on 1.1
8011H	? (lo byte)\
8012H	? (hi byte)-- 0x8792 on 1.1
8013H	ring flag2? (0 on 1.1; if 0 skips some code)

Shared:
C000H	Status (5 on reset, Master: 0 > 3 > 0 > 1 > 2 > 0 ...; 3 = copy SHARE to INT; 1 = sending; 2 = copy INT to SHARE; 8 = timeout)
C001H	mode (0 = relay, 1 = master, 2 = slave)
C002H	local node id (1 = master, 0 = relay)
C003H	total node count
C004H	? (0 on master/slave, 1 on relay)
C005H	? (?)

C006H-C00FH = shared memory (set by master)
C00EH	? (lo byte)\
C00FH	? (hi byte)-- 0x0231

Disassembly

; Disassembly of the file "epr-15112.17"
; 
; CPU Type: Z80
; 
; Created with dZ80 2.0
; 
; on Tuesday, 26 of May 2015 at 04:00 AM
; 
0000H - MAIN
# Binary ASM Comment
void main(){
	setStackPointer(0xA000);
	disableInterrupts();
	setInterruptMode(0);
	setupComm();
}
0000H3100A0LD SP,0A000HSet StackPointer to 0xA000
0003HF3DIdisable interrupts
0004HED46IM 0interrupt mode 0
0006HC3A203JP 03A2HJump to SETUP_COMM
0028H - INT5 VINT
# Binary ASM Comment
void int5(){
	byte A;

	A = 32;
	do {
		A--;
	} while(A > 0);
	memw(0x8000, memr(0x8000)--);
	enableInterrupts();
}
0028H08EX AF,AF'Exchange AF with AF'
0029H3E20LD A,20HA = 32
002BH3DDEC AA--
002CH20FDJR NZ,002BH ; (-03h)While A > 0 Jump to 002BH
002EH3A0080LD A,(8000H)A = RAM(0H)
0031H3DDEC AA --
0032H320080LD (8000H),ARAM(0H) = A
0035H08EX AF,AF'Exchange AF with AF'
0036HFBEIenable interrupts
0037HC9RETreturn
0028H - INT7 DLC
# Binary ASM Comment
void int7(){
	byte A;

	A = ior(0x08);
	A = ior(0x0F);
	A = ior(0x0C):
	if(A & 1){
		A ^= A;
		iow(0x0F, A);
	}
	enableInterrupts();
}
0038H08EX AF,AF'Exchange AF with AF'
0039HDB08IN A,(08H)read DLC 'Receive status 0'
003BHDB0FIN A,(0FH)read DLC 'Serial data'
003DHDB0CIN A,(0CH)read DLC 'Transmit status'
003FHE601AND 01Hcheck bit 0
0041H2803JR Z,0046H ; (+03h)if ZERO jump to 0046H
0043HAFXOR AXOR A
0044HD30FOUT (0FH),Awrite DLC 'Serial data'
0046H08EX AF,AF'Exchange AF with AF'
0047HFBEIenable interrupts
0048HC9RETreturn
0080H - DMA Setup [CH3 - Master?] (10 address/value pairs)
# Binary ASM Comment
0080H2A01 I/O Address 0x2A 'Single Mask Register'
0081H07value 'SRST, CH3'
0082H2C02 I/O Address 0x2C 'Clear Flip-Flop Register'
0083H00-
0084H2603 I/O Address 0x26 'Offset Register (CH3)'
0085H0Bvalue xx0B
0086H2604 I/O Address 0x26 'Offset Register (CH3)'
0087H80value 80xx
0088H2C05 I/O Address 0x2C 'Clear Flip-Flop Register'
0089H00-
008AH2706 I/O Address 0x27 'Block Size Register (CH3)'
008BH00value xx00
008CH2707 I/O Address 0x27 'Block Size Register (CH3)'
008DH00value 00xx
008EH2B08 I/O Address 0x2B 'Mode Register'
008FH0Bvalue 'MODE0, TYPE2, CH3'
0090H2A09 I/O Address 0x2A 'Single Mask Register'
0091H03value 'CH3'
0092H2810 I/O Address 0x28 'Command and Status Register'
0093H30value 'ROTATE, EXTENDED'
0094H - DMA Setup [CH2 - Master?] (10 address/value pairs)
# Binary ASM Comment
0094H2A01 I/O Address 0x2A 'Single Mask Register'
0095H06value 'SRST, CH2'
0096H2C02 I/O Address 0x2C 'Clear Flip-Flop Register'
0097H00-
0098H2403 I/O Address 0x24 'Offset Register (CH2)'
0099H0Bvalue xx0B
009AH2404 I/O Address 0x24 'Offset Register (CH2)'
009BH80value 80xx
009CH2C05 I/O Address 0x2C 'Clear Flip-Flop Register'
009DH00-
009EH2506 I/O Address 0x25 'Block Size Register (CH2)'
009FH00value xx00
00A0H2507 I/O Address 0x25 'Block Size Register (CH2)'
00A1H00value 00xx
00A2H2B08 I/O Address 0x2B 'Mode Register'
00A3H06value 'MODE0, TYPE1, CH2'
00A4H2A09 I/O Address 0x2A 'Single Mask Register'
00A5H02value 'CH2'
00A6H2810 I/O Address 0x28 'Command and Status Register'
00A7H30value 'ROTATE, EXTENDED'
00A8H - DMA Setup [CH2 - Master?] (10 address/value pairs)
# Binary ASM Comment
00A8H2A01 I/O Address 0x2A 'Single Mask Register'
00A9H06value 'SRST, CH2'
00AAH2C02 I/O Address 0x2C 'Clear Flip-Flop Register'
00ABH00-
00ACH2403 I/O Address 0x24 'Offset Register (CH2)'
00ADH0Cvalue xx0C
00AEH2404 I/O Address 0x24 'Offset Register (CH2)'
00AFH80value 80xx
00B0H2C05 I/O Address 0x2C 'Clear Flip-Flop Register'
00B1H00-
00B2H2506 I/O Address 0x25 'Block Size Register (CH2)'
00B3H00value xx00
00B4H2507 I/O Address 0x25 'Block Size Register (CH2)'
00B5H00value 00xx
00B6H2B08 I/O Address 0x2B 'Mode Register'
00B7H06value 'MODE0, TYPE1, CH2'
00B8H2A09 I/O Address 0x2A 'Single Mask Register'
00B9H02value 'CH2'
00BAH2810 I/O Address 0x28 'Command and Status Register'
00BBH30value 'ROTATE, EXTENDED'
00BCH - DMA Setup [CH3 - Master] (10 address/value pairs)
# Binary ASM Comment
00BCH2A01 I/O Address 0x2A 'Single Mask Register'
00BDH07value 'SRST, CH3'
00BEH2C02 I/O Address 0x2C 'Clear Flip-Flop Register'
00BFH00-
00C0H2603 I/O Address 0x26 'Offset Register (CH3)'
00C1H06value xx06
00C2H2604 I/O Address 0x26 'Offset Register (CH3)'
00C3HC0value C0xx
00C4H2C05 I/O Address 0x2C 'Clear Flip-Flop Register'
00C5H00-
00C6H2706 I/O Address 0x27 'Block Size Register (CH3)'
00C7H09value xx09
00C8H2707 I/O Address 0x27 'Block Size Register (CH3)'
00C9H00value 00xx
00CAH2B08 I/O Address 0x2B 'Mode Register'
00CBH0Bvalue 'MODE0, TYPE2, CH3'
00CCH2A09 I/O Address 0x2A 'Single Mask Register'
00CDH03value 'CH3'
00CEH2810 I/O Address 0x28 'Command and Status Register'
00CFH30value 'ROTATE, EXTENDED'
00D0H - DMA Setup [CH2 - Master] (10 address/value pairs)
# Binary ASM Comment
00D0H2A01 I/O Address 0x2A 'Single Mask Register'
00D1H06value 'SRST, CH2'
00D2H2C02 I/O Address 0x2C 'Clear Flip-Flop Register'
00D3H00-
00D4H2403 I/O Address 0x24 'Offset Register (CH2)'
00D5H06value xx06
00D6H2404 I/O Address 0x24 'Offset Register (CH2)'
00D7HC0value C0xx
00D8H2C05 I/O Address 0x2C 'Clear Flip-Flop Register'
00D9H00-
00DAH2506 I/O Address 0x25 'Block Size Register (CH2)'
00DBH09value xx09
00DCH2507 I/O Address 0x25 'Block Size Register (CH2)'
00DDH00value 00xx
00DEH2B08 I/O Address 0x2B 'Mode Register'
00DFH06value 'MODE0, TYPE1, CH2'
00E0H2A09 I/O Address 0x2A 'Single Mask Register'
00E1H02value 'CH2'
00E2H2810 I/O Address 0x28 'Command and Status Register'
00E3H30value 'ROTATE, EXTENDED'
00E4H - DMA Setup [CH2 - Master] (10 address/value pairs) (unused?)
# Binary ASM Comment
00E4H2A01
00E5H06
00E6H2C02
00E7H00
00E8H2403
00E9H00
00EAH2404
00EBH84
00ECH2C05
00EDH00
00EEH2506
00EFH09
00F0H2507
00F1H00
00F2H2B08
00F3H06
00F4H2A09
00F5H02
00F6H2810
00F7H30
00F8H - DMA Setup [CH0, CH1] (19 address/value pairs)
# Binary ASM Comment
00F8H2F01 I/O Address 0x2F 'Master Mask Register'
00F9H0Fvalue
00FAH2C02 I/O Address 0x2C 'Clear Flip-Flop Register'
00FBH00-
00FCH2003 I/O Address 0x20 'Offset Register CH0'
00FDH10value xx10
00FEH2004 I/O Address 0x20 'Offset Register CH0'
00FFHC0value C0xx
0100H2C05 I/O Address 0x2C 'Clear Flip-Flop Register'
0101H00-
0102H2106 I/O Address 0x21 'Block Size Register'
0103HC3value xxC3
0104H2107 I/O Address 0x21 'Block Size Register'
0105H01value 01xx
0105H2C08 I/O Address 0x2C 'Clear Flip-Flop Register'
0105H00-
0108H2209 I/O Address 0x22 'Offset Register CH1'
0109H0Avalue xx0A
010AH2210 I/O Address 0x22 'Offset Register CH1'
010BH84value 84xx
010CH2C11 I/O Address 0x2C 'Clear Flip-Flop Register'
010DH00-
010EH2312 I/O Address 0x23 'Block Size Register'
010FHC3value xxC3
010FH2313 I/O Address 0x23 'Block Size Register'
010FH01value 01xx
0112H2B14 I/O Address 0x2B 'Mode Register'
0113H88value 'MODE2, TYPE2, CH0'
0114H2B15 I/O Address 0x2B 'Mode Register'
0115H85value 'MODE2, TYPE1, CH1'
0116H2A16 I/O Address 0x2A 'Single Mask Register'
0117H00value 'CH0'
0118H2A17 I/O Address 0x2A 'Single Mask Register'
0119H01value 'CH1'
011AH2818 I/O Address 0x28 'Command and Status Register'
011BH31value
011CH2919 I/O Address 0x29 'Request Register'
011DH04value
011EH - DLC Setup (12/16 address/value pairs)
# Binary ASM Comment
011EH1701 I/O Address 0x17 'Mask'
011FHC7value 'MTXDRQ, MRXDRQ, MMODEM, MTX, MRX'
0120H0E02 I/O Address 0x0E 'Transmit interrupt enable'
0121H00value (all off)
0122H0D03 I/O Address 0x0D 'Transmit control'
0123H08value 'TXRST'
0124H0B04 I/O Address 0x0B 'Receive interrupt enable'
0125H00value (all off)
0126H0A05 I/O Address 0x0A 'Receive control'
0127H03value 'HUNT, STC'
0128H1A06 I/O Address 0x1A 'BRG1 divide value'
0129H03value 'DIV1, DIV0'
012AH1907 I/O Address 0x19 'BRG1/DPLL control'
012BH00value (all off)
012CH0008 I/O Address 0x00 'Protocol select'
012DH02value 'PS1'
012EH0109 I/O Address 0x01 'CRC select'
012FH0Cvalue 'CRCM1, CRCM0'
0130H0210 I/O Address 0x02 'Transfer mode'
0131H21value 'CODE1, TXC0'
0132H1411 I/O Address 0x14 'Transmit mode'
0133H02value 'TXUEND'
0134H0712 I/O Address 0x07 'Modem control'
0135H00value (all off)
0136H0B13 I/O Address 0x0B 'Receive interrupt enable'
0137H80value 'RXD/I'
0138H0A14 I/O Address 0x0A 'Receive control'
0139H80value 'RXE'
013AH0E15 I/O Address 0x0E 'Transmit interrupt enable'
013BH80value 'TXD/I'
013CH0D16 I/O Address 0x0D 'Transmit control'
013DH80value 'TXE'
013EH - DMA Setup (3 address/value pairs)
# Binary ASM Comment
013EH2D01 I/O Address 0x2D 'Master Reset Register'
013FH00value
0140H2F01 I/O Address 0x2F 'MultiChannel Mask Register'
0141H0Fvalue
0142H2801 I/O Address 0x28 'Status Register'
0143H28value
0144H - FRAME OFFSET TABLE (referenced by 04A7H)
# Binary ASM Comment
0144H54ring size = 0; 0x0154
0145H01-
0146H54ring size = 1; 0x0154
0147H01-
0148H56ring size = 2; 0x0156
0149H01-
014AH5Aring size = 3; 0x015A
014BH01-
014CH60ring size = 4; 0x0160
014DH01-
014EH68ring size = 5; 0x0168
014FH01-
0150H72ring size = 6; 0x0172
0151H01-
0152H7Ering size = 7; 0x017E
0153H01-
0154H8Cring size = 8; 0x018C
0155H01-
0156H9E1.1 0x019E
0155H01-
0158HA52.1 0x01A5
0159H01-
015AHB22.2 0x01B2
015BH01-
015CHBF3.1 0x01BF
015DH01-
015EHCC3.2 0x01CC
015FH01-
0160HD93.3 0x01D9
0161H01-
0162HE64.1 0x01E6
0163H01-
0164HF34.2 0x01F3
0165H01-
0166H004.3 0x0200
0167H02-
0168H0D4.4 0x020D
0169H02-
016AH1A5.1 0x021A
016BH02-
016CH275.2 0x0227
016DH02-
016EH345.3 0x0234
016FH02-
0170H415.4 0x0241
0171H02-
0172H4E5.5 0x024E
0173H02-
0174H5B6.1 0x025B
0175H02-
0176H686.2 0x0268
0177H02-
0178H756.3 0x0275
0179H02-
017AH826.4 0x0282
017BH02-
017CH8F6.5 0x028F
017DH02-
017EH9C6.6 0x029C
017FH02-
0180HA97.1 0x02A9
0181H02-
0182HB67.2 0x02B6
0183H02-
0184HC37.3 0x02C3
0185H02-
0186HD07.4 0x02D0
0187H02-
0188HDD7.5 0x02DD
0189H02-
018AHEA7.6 0x02EA
018BH02-
018CHF77.7 0x02F7
018DH02-
018EH048.1 0x0304
018FH03-
0190H118.2 0x0311
0191H03-
0192H1E8.3 0x031E
0193H03-
0194H2B8.4 0x032B
0195H03-
0196H388.5 0x0338
0197H03-
0198H458.6 0x0345
0199H03-
019AH528.7 0x0352
019BH03-
019CH5F8.8 0x035F
019DH03-
019EH00?? 0
019FH0A0x840A
01A0H84-
01A1HD40xC1D4
01A2HC1
01A3HC30x01C3
01A4H01-
01A5H01?? 1
01A6H0A0x840A
01A7H84--
01A8HD40xC1D4
01A9HC1-
01AAHC30x01C3
01ABH01
01ACHCE0x85CE
01ADH85-
01AEH980xC398
01AFHC3-
01B0HC30x01C3
01B1H01-
01B2H01?? 1
01B3H0A0x840A
01B4H84-
01B5H980xC398
01B6HC3-
01B7HC30x01C3
01B8H01-
01B9HCE0x85CE
01BAH85-
01BBHD40xC1D4
01BCHC1-
01BDHC30x01C3
01BEH01-
01BFH01?? 1
01C0H0A0x840A
01C1H84-
01C2HD40xC1D4
01C3HC1-
01C4HC30x01C3
01C5H01-
01C6HCE0x85CE
01C7H85-
01C8H980xC398
01C9HC3
01CAH870x0387
01CBH03-
01CCH010A84LD BC,840AH
01CFH98SBC A,B
01D0HC38703JP 0387H
01D3H92SUB D
01D4H87ADD A,A
01D5HD4C1C3
01D8H01010ALD BC,0A01H
01DBH84ADD A,H
01DCH5CLD E,H
01DDHC5PUSH BC
01DEHC301CEJP 0CE01H
01E1H85ADD A,L
01E2HD4C187CALL NC,87C1H
01E5H03INC BC
01E6H010A84LD BC,840AH
01E9HD4C1C3
01ECH01CE85LD BC,85CEH
01EFH98SBC A,B
01F0HC34B05JP 054BH
01F3H010A84LD BC,840AH
01F6H98SBC A,B
01F7HC34B05JP 054BH
01FAH56LD D,(HL)
01FBH89ADC A,C
01FCHD4- C1D4
01FDHC1-
01FEHC3
01FFH01010ALD BC,0A01H
0202H84- 5C84
0203H5C
0204HC5PUSH BC
0205H87ADD A,A
0206H03INC BC
0207H92SUB D
0208H87ADD A,A
0209HD4C187CALL NC,87C1H
020CH03INC BC
020DH010A84LD BC,840AH
0210H20C7JR NZ,01D9H ; (-39h)
0212HC301CEJP 0CE01H
0215H85ADD A,L
0216HD4C14BCALL NC,4BC1H
0219H05DEC B
021AH010A84LD BC,840AH
021DHD4C1C3
0220H01CE85LD BC,85CEH
0223H98SBC A,B
0224HC30F07JP 070FH
0227H010A84LD BC,840AH
022AH98SBC A,B
022BHC30F07JP 070FH
022EH1ALD A,(DE)
022FH8BADC A,E
0230HD4C1C3
0233H01010ALD BC,0A01H
0236H84ADD A,H
0237H5CLD E,H
0238HC5PUSH BC
0239H4BLD C,E
023AH05DEC B
023BH56LD D,(HL)
023CH89ADC A,C
023DHD4C187CALL NC,87C1H
0240H03INC BC
0241H010A84LD BC,840AH
0244H20C7JR NZ,020DH ; (-39h)
0246H87ADD A,A
0247H03INC BC
0248H92SUB D
0249H87ADD A,A
024AHD4C14BCALL NC,4BC1H
024DH05DEC B
024EH010A84LD BC,840AH
0251HE4C8C3CALL PO,0C3C8H
0254H01CE85LD BC,85CEH
0257HD4C10FCALL NC,0FC1H
025AH07RLCA
025BH010A84LD BC,840AH
025EHD4C1C3
0261H01CE85LD BC,85CEH
0264H98SBC A,B
0265HC3D308JP 08D3H
0268H010A84LD BC,840AH
026BH98SBC A,B
026CHC3D308JP 08D3H
026FHDE8CSBC A,8CH
0271HD4C1C3
0274H01010ALD BC,0A01H
0277H84ADD A,H
0278H5CLD E,H
0279HC5PUSH BC
027AH0FRRCA
027BH07RLCA
027CH1ALD A,(DE)
027DH8BADC A,E
027EHD4C187CALL NC,87C1H
0281H03INC BC
0282H010A84LD BC,840AH
0285H20C7JR NZ,024EH ; (-39h)
0287H4BLD C,E
0288H05DEC B
0289H56LD D,(HL)
028AH89ADC A,C
028BHD4C14BCALL NC,4BC1H
028EH05DEC B
028FH010A84LD BC,840AH
0292HE4C887CALL PO,87C8H
0295H03INC BC
0296H92SUB D
0297H87ADD A,A
0298HD4C10FCALL NC,0FC1H
029BH07RLCA
029CH010A84LD BC,840AH
029FHA8XOR B
02A0HCAC301JP Z,01C3H
02A3HCE85ADC A,85H
02A5HD4C1D3CALL NC,0D3C1H
02A8H08EX AF,AF'
02A9H010A84LD BC,840AH
02ACHD4C1C3
02AFH01CE85LD BC,85CEH
02B2H98SBC A,B
02B3HC3970AJP 0A97H
02B6H010A84LD BC,840AH
02B9H98SBC A,B
02BAHC3970AJP 0A97H
02BDHA2AND D
02BEH8EADC A,(HL)
02BFHD4C1C3
02C2H01010ALD BC,0A01H
02C5H84ADD A,H
02C6H5CLD E,H
02C7HC5PUSH BC
02C8HD308OUT (08H),A
02CAHDE8CSBC A,8CH
02CCHD4C187CALL NC,87C1H
02CFH03INC BC
02D0H010A84LD BC,840AH
02D3H20C7JR NZ,029CH ; (-39h)
02D5H0FRRCA
02D6H07RLCA
02D7H1ALD A,(DE)
02D8H8BADC A,E
02D9HD4C14BCALL NC,4BC1H
02DCH05DEC B
02DDH010A84LD BC,840AH
02E0HE4C84BCALL PO,4BC8H
02E3H05DEC B
02E4H56LD D,(HL)
02E5H89ADC A,C
02E6HD4C10FCALL NC,0FC1H
02E9H07RLCA
02EAH010A84LD BC,840AH
02EDHA8XOR B
02EEHCA8703JP Z,0387H
02F1H92SUB D
02F2H87ADD A,A
02F3HD4C1D3CALL NC,0D3C1H
02F6H08EX AF,AF'
02F7H010A84LD BC,840AH
02FAH6CLD L,H
02FBHCCC301CALL Z,01C3H
02FEHCE85ADC A,85H
0300HD4C197CALL NC,97C1H
0303H0ALD A,(BC)
0304H010A84LD BC,840AH
0307HD4C1C3
030AH01CE85LD BC,85CEH
030DH98SBC A,B
030EHC35B0CJP 0C5BH
0311H010A84LD BC,840AH
0314H98SBC A,B
0315HC35B0CJP 0C5BH
0318H66LD H,(HL)
0319H90SUB B
031AHD4C1C3
031DH01010ALD BC,0A01H
0320H84ADD A,H
0321H5CLD E,H
0322HC5PUSH BC
0323H97SUB A
0324H0ALD A,(BC)
0325HA2AND D
0326H8EADC A,(HL)
0327HD4C187CALL NC,87C1H
032AH03INC BC
032BH010A84LD BC,840AH
032EH20C7JR NZ,02F7H ; (-39h)
0330HD308OUT (08H),A
0332HDE8CSBC A,8CH
0334HD4C14BCALL NC,4BC1H
0337H05DEC B
0338H010A84LD BC,840AH
033BHE4C80FCALL PO,0FC8H
033EH07RLCA
033FH1ALD A,(DE)
0340H8BADC A,E
0341HD4C10FCALL NC,0FC1H
0344H07RLCA
0345H010A84LD BC,840AH
0348HA8XOR B
0349HCA4B05JP Z,054BH
034CH56LD D,(HL)
034DH89ADC A,C
034EHD4C1D3CALL NC,0D3C1H
0351H08EX AF,AF'
0352H010A84LD BC,840AH
0355H6CLD L,H
0356HCC8703CALL Z,0387H
0359H92SUB D
035AH87ADD A,A
035BHD4C197CALL NC,97C1H
035EH0ALD A,(BC)
035FH01?? 1
0360H0A0x840A
0361H84-
0362H300xCE30
0363HCE-
0364HC30x01C3
0365H01-
0366HCE0x85CE
0367H85-
0368HD40xC1D4
0369HC1-
036AH5B0x0C5B
036BH0C-
036CH00NOP
036DH00NOP
036EHC30100JP 0001H
0371H00NOP
0372H00NOP
0373H00NOP
0374HC30100JP 0001H
0377H00NOP
0378H00NOP
0379H01C301LD BC,01C3H
037CHC30100JP 0001H
037FH018703LD BC,0387H
0382HC30100JP 0001H
0385H014B05LD BC,054BH
0388HC30100JP 0001H
038BH014B05LD BC,054BH
038EH87ADD A,A
038FH03INC BC
0390H00NOP
0391H014B05LD BC,054BH
0394H4BLD C,E
0395H05DEC B
0396H00NOP
0397H014B05LD BC,054BH
039AH0FRRCA
039BH07RLCA
039CH00NOP
039DH014B05LD BC,054BH
03A0HD308OUT (08H),A
03A2H - SETUP_COMM
# Binary ASM Comment
void setupComm(){
	byte A;

	resetComm();
	zeroInternalMemory();
	testVInt120();

	resetComm();

	A = memr(0xC001);
	A--;
	if (A == 0){
		// Master
		setupRingMaster();
		copyAndConfigDma();
		waitVInt();
		syncCommon150();
		loopMaster();
	} else {
		// Slave & Relay
		setupRingSlaveRelay();
		copyAndConfigDma();
		readCommon150();
		loopSlaveRelay();
	}
}
03A2HCD0304CALL 0403HCall RESET_COMM
03A5HCD5604CALL 0456HCall ZERO_INTERNAL_MEMORY
03A8HCD3B04CALL 043BHCall TEST_VINT_120
03ABHCD0304CALL 0403HCall RESET_COMM
03AEH3A01C0LD A,(0C001H)A = SHARE(0x0001); 0 = Relay, 1 = Master, 2 = Slave
03B1H3DDEC AA--
03B2HCAC503JP Z,03C5HIf ZERO jump to 03C5H ; Master only
03B5HAFXOR AA ^= A (=0)
03B6HD340OUT (40H),Awrite A to SYN
03B8HF3DIdisable interrupts
03B9HCD5A06CALL 065AHCall SETUP_RING_SLAVE_RELAY
03BCHCD6004CALL 0460HCall COPY_AND_CONFIGURE_DMA
03BFHCDE703CALL 03E7HCall READ_COMMON_150
03C2HC34108JP 0841HJump to LOOP_SLAVE_RELAY
03C5HCDB905CALL 05B9HCall SETUP_RING_MASTER
03C8HCD6004CALL 0460HCall COPY_AND_CONFIGURE_DMA
03CBHCDAA05CALL 05AAHCall WAIT_VINT
03CEHCDD403CALL 03D4HCall SYNC_COMMON_150
03D1HC35707JP 0757HJump to LOOP_MASTER
03D4H - SYNC_COMMON_150
# Binary ASM Comment
void syncCommon150(){
	byte A;

	A = 0x96; // 150
	memw(0x8001, A);

	do {
		syncCommon();
		A = memr(0x8001);
		A--;
		memw(0x8001, A);
	} while (A > 0);
}
03D4H3E96LD A,96HA = 150
03D6H320180LD (8001H),AMEM(0x0001) = A
03D9HCDBA07CALL 07BAHCall SYNC_COMMON
03DCH3A0180LD A,(8001H)A = MEM(0x0001)
03DFH3DDEC AA--
03E0H320180LD (8001H),AMEM(0x0001) = A
03E3HC2D903JP NZ,03D9HIf NOT ZERO jump to 03D9H
03E6HC9RETreturn
03E7H - READ_COMMON_150
# Binary ASM Comment
03E7H3E96LD A,96HA = 0x150
03E9H320180LD (8001H),AMEM(0x0001) = A
03ECHCDCB08CALL 08CBHCall READ_COMMON
03EFH3A0180LD A,(8001H)A = MEM(0x0001)
03F2H3DDEC AA--
03F3H320180LD (8001H),AMEM(0x0001) = A
03F6HC2EC03JP NZ,03ECHIf NOT ZERO jump to 03ECH
03F9HC9RETreturn
03FAH - ZERO_MEMORY
# Binary ASM Comment
void zeroMemory(int HL, int BC){
	int DE;

	memw(HL, 0x00);

	DE = HL;
	DE++;
	BC--;

	while (BC > 0){
		memw(DE, memr(HL));
		DE++;
		HL++;
		BC--;
	}
}
03FAH3600LD (HL),00H*HL* = 0
03FCH54LD D,HD = H
03FDH5DLD E,LE = L
03FEH13INC DEDE++
03FFH0BDEC BCBC--
0400HEDB0LDIRwhile BC > 0 (*DE* = *HL*, DE++, HL++, BC--)
0402HC9RETreturn
0403H - RESET_COMM
# Binary ASM Comment
void resetComm(){
	memw(0xC000, 5);

	resetDlc();
	resetDma();

	iow(0x60, 0);
	iow(0x40, 0);

	memw(0x800E, 0);
	memw(0x8006, 0);
	memw(0x8007, 0);
	memw(0x8003, 2);

	// 0 = relay, 1 = master, 2 = slave
	byte a = memr(0xC001);

	if (a == 0) {
		// relay
		memw(0x8007, 1);
		memw(0xC004, 1);
		return;
	}

	a--;
	if (a == 0) {
		// master
		return;
	} else {
		// slave
		memw(0x8006, 1);
		return;
	}
}
0403H3E05LD A,05HA = 5
0405H3200C0LD (0C000H),ASHARE(0x0000) = A
0408HCD8605CALL 0586HCall RESET_DLC
040BHCD9D05CALL 059DHCall RESET_DMA
040EHAFXOR AA ^= A (=0)
040FHD360OUT (60H),Awrite ZFG
0411HD340OUT (40H),Awrite SYN
0413H320E80LD (800EH),AMEM(0x000E) = A
0416H320680LD (8006H),AMEM(0x0006) = A
0419H320780LD (8007H),AMEM(0x0007) = A
041CH3E02LD A,02HA = 2
041EH320380LD (8003H),AMEM(0x0003) = A
0421H3A01C0LD A,(0C001H)A = SHARE(0x0001)
0424HB7OR AOR A
0425HCA3204JP Z,0432HIf A = 0 jump to 0432H
0428H3DDEC AA--
0429HCA3A04JP Z,043AHIf A = 0 jump to 043AH
042CH3E01LD A,01HA = 1
042EH320680LD (8006H),AMEM(0x0006) = A
0431HC9RETreturn
0432H3E01LD A,01HA = 1
0434H320780LD (8007H),AMEM(0x0007) = A
0437H3204C0LD (C004H),ASHARE(0x0004) = A
043AHC9RETreturn
043BH - TEST_VINT_120 (waits for 120 VINTs)
# Binary ASM Comment
void testVInt120(){
	byte A = 120;
	memw(0x8001, A);
	
	do {
		waitVInt();
		A = memr(0x8001)
		A--
		memw(0x8001, A);
	} while(A > 0);
}
043BH3E78LD A,78HA = 0x78
043DH320180LD (8001H),AMEM(0x0001) = A
0440HCDA605CALL 05A6HCall 05A6H
0443H3A0180LD A,(8001H)A = MEM(0x0001)
0446H3DDEC AA--
0447H320180LD (8001H),AMEM (0x0001) = A
044AHC24004JP NZ,0440HIf NOT ZERO jump to 0440H
044DHC9RET
044EH - SETUP_REGISTERS (copy B address/value pairs from HL)
# Binary ASM Comment
void setupRegisters(int HL, int B){
	byte C;
	do {
		C = memr(HL);
		HL++;
		iow(C, memr(HL));
		B--;
	} while (B > 0);
}
044EH4ELD C,(HL)C = *HL*
044FH23INC HLHL++
0450HEDA3OUTIread from HL, write to C, decrease B
0452HC24E04JP NZ,044EHwhile B > 0 jump to 044EH
0455HC9RETreturn
0456H - ZERO_INTERNAL_MEMORY
# Binary ASM Comment
void zeroInternalMemory(){
	zeroMemory(0x8000, 0x1FF0);
}
0456H210080LD HL,8000HHL = 0x8000
0459H01F01FLD BC,1FF0HBC = 0x1FF0
045CHCDFA03CALL 03FAHCall ZERO_MEMORY
045FHC9RETreturn
0460H - COPY_AND_CONFIGURE_DMA
# Binary ASM Comment
0460H218000LD HL,0080HHL = 0x0080
0463H11C080LD DE,80C0HDE = 0x80C0
0466H011400LD BC,0014HBC = 0x0014
0469HEDB0LDIRcopy 0x0014 bytes from 0x0080 to 0x80C0; DMA Config CH3
046BH219400LD HL,0094HHL = 0x0094
046EH11A080LD DE,80A0HDE = 0x80A0
0471H011400LD BC,0014HBC = 0x0014
0474HEDB0LDIRcopy 0x0014 bytes from 0x0094 to 0x80A0; DMA Config CH2
0476H218000LD HL,0080HHL = 0x0080
0479H110081LD DE,8100HDE = 0x8100
047CH011400LD BC,0014HBC = 0x0014
047FHEDB0LDIRcopy 0x0014 bytes from 0x0080 to 0x8100; DMA Config CH3
0481H219400LD HL,0094HHL = 0x0094
0484H11E080LD DE,80E0HDE = 0x80E0
0487H011400LD BC,0014HBC = 0x0014
048AHEDB0LDIRcopy 0x0014 bytes from 0x0094 to 0x80E0; DMA Config CH2
048CH21F800LD HL,00F8HHL = 0x00F8
048FH114080LD DE,8040HDE = 0x8040
0492H012600LD BC,0026HBC = 0x0026
0495HEDB0LDIRcopy 0x0026 bytes from 0x00F8 to 0x8040
0497H21F800LD HL,00F8HHL = 0x00F8
049AH117080LD DE,8070HDE = 0x8070
049DH012600LD BC,0026HBC = 0x0026
04A0HEDB0LDIRcopy 0x0026 bytes from 0x00F8 to 0x8070
04A2H3A0880LD A,(8008H)A = MEM(0x0008); total node count
04A5H87ADD A,AA += A
04A6H4FLD C,AC = A
04A7H214401LD HL,0144HHL = 0x0144
04AAH09ADD HL,BCHL += BC; HL = 0x146 on 1.x
04ABH7ELD A,(HL)A = *HL*
04ACH23INC HLHL++
04ADH66LD H,(HL)H = *HL*
04AEH6FLD L,AL = A; HL = 0x0154 on 1.x
04AFH3A0980LD A,(8009H)A = MEM(0x0009); local node id
04B2H87ADD A,AA += A
04B3H5FLD E,AE = A
04B4H1600LD D,00HD = 0x00
04B6H19ADD HL,DEHL += DE; HL = 0x156 on 1.1
04B7H7ELD A,(HL)A = *HL*
04B8H23INC HLHL++
04B9H66LD H,(HL)H = *HL*
04BAH6FLD L,AL = A; HL = 0x019E on 1.1
04BBH7ELD A,(HL)A = *HL*; A = 0x00 on 1.1
04BCH320A80LD (800AH),AMEM(0x000A) = A
04BFH0602LD B,02HB = 0x02
04C1HDD214080LD IX,8040HIX = 0x8040
04C5H23INC HLHL++; 0x19F on 1.1a, 0x01A5 on 1.1b
04C6H7ELD A,(HL)A = *HL*; 0x0A on 1.1a, 0x01 on 1.1b
04C7HDD7705LD (IX+05H),AMEM(IX+0x05) = A
04CAH23INC HLHL++; 0x01A0 on 1.1a, 0x01A6 on 1.1b
04CBH7ELD A,(HL)A = *HL*; 0x84 on 1.1a, 0x0A on 1.1b
04CCHDD7707LD (IX+07H),AMEM(IX+0x07) = A
04CFH23INC HLHL++; 0x01A1 on 1.1a, 0x01A7 on 1.1b
04D0H7ELD A,(HL)A = *HL*; 0xD4 on 1.1a, 0x84 on 1.1b
04D1HDD7711LD (IX+11H),AMEM(IX+0x11) = A
04D4H23INC HLHL++; HL = 0x01A2 on 1.1a, 0x01A8 on 1.1b
04D5H7ELD A,(HL)A = *HL*; 0xC1 on 1.1a, 0xD4 on 1.1b
04D6HDD7713LD (IX+13H),AMEM(IX+0x13) = A
04D9H23INC HLHL++; 0x01A3 on 1.1a, 0x01A9 on 1.1b
04DAH7ELD A,(HL)A = *HL*; 0xC3 on 1.1a, 0xC1 on 1.1b
04DBHDD770BLD (IX+0BH),AMEM(IX+0x0B) = A
04DEHDD7717LD (IX+17H),AMEM(IX+0x17) = A
04E1H23INC HLHL++; 0x01A4 on 1.1a, 0x01AA on 1.1b
04E2H7ELD A,(HL)A = *HL*; 0x01 on 1.1a, 0xC3 on 1.1b
04E3HDD770DLD (IX+0DH),AMEM(IX+0x0D) = A
04E6HDD7719LD (IX+19H),AMEM(IX+0x19) = A
04E9HDD217080LD IX,8070HIX = 0x8070
04EDH10D6DJNZ 04C5H ; (-2ah)B--; If B > 0 jump to 04C5H
04EFHDD21C080LD IX,80C0H
04F3HFD21A080LD IY,80A0H
04F7H216D03LD HL,036DHHL = 0x36D
04FAH09ADD HL,BCHL += BC
04FBH09ADD HL,BCHL += BC
04FCH09ADD HL,BCHL += BC; BC = 0x02 on 1.1; HL = 0x0373 on 1.1
04FDH7ELD A,(HL)A = *HL*; 0x00 on 1.1
04FEH321380LD (8013H),AMEM(0x0013H) = A
0501H23INC HLHL++; 0x0374 on 1.1
0502H4ELD C,(HL)C = *HL*; 0xC3 on 1.1
0503HDD710BLD (IX+0BH),C
0506HFD710BLD (IY+0BH),C
0509H23INC HLHL++; 0x0375 on 1.1
050AH46LD B,(HL)B = *HL*; 0x01 on 1.1
050BHDD700DLD (IX+0DH),B
050EHFD700DLD (IY+0DH),B
0511H23INC HLHL++; 0x0376 on 1.1
0512H03INC BCBC++; 0x01C4 on 1.1
0513HEBEX DE,HLExchange DE and HL
0514H210A84LD HL,840AHHL = 0x840A
0517HDD7505LD (IX+05H),L
051AHDD7407LD (IX+07H),H
051DHDD210081LD IX,8100H
0521H09ADD HL,BCHL += BC; HL = 0x85CE on 1.1
0522HDD7505LD (IX+05H),L
0525HDD7407LD (IX+07H),H
0528H3A0780LD A,(8007H)A = MEM(0x0007)
052BHB7OR AA |= A
052CH201CJR NZ,054AH ; (+1ch)If NOT ZERO jump to 054AH; 1 = Relay, 0 = Master/Slave
052EH21CE85LD HL,85CEHHL = 0x85CE; start master/slave
0531H220F80LD (800FH),HLMEM(0x000F) = L; MEM(0x0010) = H;
0534HFD7505LD (IY+05H),L
0537HFD7407LD (IY+07H),H
053AHFD21E080LD IY,80E0H
053EH09ADD HL,BCHL += BC; HL = 0x8792 on 1.1; BC = 0x01C4 on 1.1
053FHFD7505LD (IY+05H),L
0542HFD7407LD (IY+07H),H
0545H221180LD (8011H),HLMEM(0x0011) = L; MEM(0x0012) = H
0548H1822JR 056CH ; (+22h)Jump to 056CH; end of master/slave
054AH210A84LD HL,840AH; start relay
054DHFD7505LD (IY+05H),L
0550HFD7407LD (IY+07H),H
0553HFD21E080LD IY,80E0H
0557H09ADD HL,BC
0558HFD7505LD (IY+05H),L
055BHFD7407LD (IY+07H),H
055EH217A84LD HL,847AH
0561H220F80LD (800FH),HL
0564H09ADD HL,BC
0565H221180LD (8011H),HL
0568HAFXOR A
0569H3202C0LD (0C002H),A; end of relay
056CH1ALD A,(DE); DE = 0x0376 on 1.1; A = 0x00 on 1.1
056DHDD770BLD (IX+0BH),A
0570HFD770BLD (IY+0BH),A
0573H13INC DE; DE = 0x0377 on 1.1
0574H1ALD A,(DE); A = 0x00 on 1.1
0575HDD770DLD (IX+0DH),A
0578HFD770DLD (IY+0DH),A
057BH3E01LD A,01HA = 0x01
057DHD360OUT (60H),Awrite A to ZFG
057FH213102LD HL,0231HHL = 0x0231
0582H220EC0LD (0C00EH),HLSHARE(0x000E) = L; SHARE(0x000F) = H
0585HC9RETreturn
0586H - RESET_DLC
# Binary ASM Comment
void resetDlc(){
	ior(0x0C);
	iow(0x0C, 0x60);

	for(b=0x10;b>0;b--){
		ior(0x08);
		ior(0x0F);
	}

	setupRegisters(0x011E, 0x0C);
}
0586HDB0CIN A,(0CH)read DLC 'Transmit status'
0588H3E60LD A,60HA = 0x60
058AHD30COUT (0CH),Awrite DLC 'Transmit status'
058CH0610LD B,10HB = 0x10
058EHDB08IN A,(08H)read DLC 'Receive status 0'
0590HDB0FIN A,(0FH)read DLC 'Serial data'
0592H10FADJNZ 058EH ; (-06h)B--; if (B != 0) jump to 058EH
0594H211E01LD HL,011EHHL = 0x011E
0597H060CLD B,0CHB = 0x0C
0599HCD4E04CALL 044EHCall 044EH
059CHC9RETreturn
059DH - RESET_DMA
# Binary ASM Comment
void resetDma(){
	setupRegisters(0x013E, 0x03);
}
059DH213E01LD HL,013EHHL = 0x013E
05A0H0603LD B,03HB = 0x03
05A2HCD4E04CALL 044EHCall 044EH
05A5HC9RETreturn
05A6H - WAIT_VINT
# Binary ASM Comment
void waitVInt(){
	byte a = 2;
	iow(0x40, a); // enable vint

	a ^= a;       // 2 ^ 2 = 0?
	memw(0x8000, a);
	enableIrqs();

	hl = 0x8000;
	while (memr(hl) - a == 0){}

	memw(hl, a);
}
05A6H3E02LD A,02HA = 2
05A8HD340OUT (40H),Awrite A to SYN
05AAHAFXOR AA ^= A (=0)
05ABH320080LD (8000H),AMEM(0x0000) = A
05AEHFBEIenable interrupts
05AFH210080LD HL,8000HHL = 0x8000
05B2HAFXOR AA ^= A (=0)
05B3HBECP (HL)X = A - *HL*
05B4HCAB305JP Z,05B3HIf ZERO jump to 05B3H
05B7H77LD (HL),A*HL* = A
05B8HC9RETreturn
05B9H - SETUP_RING_MASTER
# Binary ASM Comment
void setupRingMaster(){
	byte A;
	byte R;

	ior(0x08);

	setupRegisters(0x011E, 0x10);

	iow(0x40, 0x02); // enable vint

	A = 0x4B;
	do {
		R = sendByteBeforeVInt(A);
	} while(R != A);

	wait255();

	A = 0x61;
	do {
		R = sendByteBeforeVInt(A);
	} while(R != A);

	wait255();

	A = 0x7A;
	do {
		R = sendByteBeforeVInt(A);
	} while(R != A);

	waitVInt;
	wait255();

	do {
		R = sendByteBeforeVInt(A);
	} while(R != A);

	waitVInt;
	wait255();

	A = 0x01;
	memw(0x8009) = A;
	memw(0xC002) = A; // this is the node id

	R = sendByteBeforeVInt(A);
	memw(0x8008) = R;
	memw(0xC003) = R; // this is the node count

	waitVInt;
	wait255();

	A = memr(0x8008);
	R = sendByteBeforeVInt(A);

	flushRXTX();

	disableRXTX();

	validateRingSize();
}
05B9HDB08IN A,(08H)read DLC 'Receive status 0'
05BBH211E01LD HL,011EHHL = 0x011E
05BEH0610LD B,10HB = 0x10
05C0HCDF409CALL 09F4HCall SETUP_REGISTERS_HL_B
05C3H3E02LD A,02HA = 2
05C5HD340OUT (40H),Awrite A to SYN
05C7H3E4BLD A,4BHA = 0x4B
05C9HCD2006CALL 0620HCall SEND_BYTE_BEFORE_VINT
05CCHFE4BCP 4BHx = A - 0x4B
05CEHC2C705JP NZ,05C7HIf NOT ZERO jump to 05C7H; loop to test if A gets sent over the ring before a VINT happens.
05D1HCD4307CALL 0743HCall WAIT_255
05D4H3E61LD A,61HA = 0x61
05D6HCD2006CALL 0620HCall SEND_BYTE_BEFORE_VINT
05D9HFE61CP 61Hx = A - 0x61
05DBHC2D405JP NZ,05D4HIf NOT ZERO jump to 05D4H; loop to test if A gets sent over the ring before a VINT happens.
05DEHCD4307CALL 0743HCall WAIT_255
05E1H3E7ALD A,7AHA = 0x7A
05E3HCD2006CALL 0620HCall SEND_BYTE_BEFORE_VINT
05E6HFE7ACP 7AHx = A - 0x7A
05E8HC2E105JP NZ,05E1HIf NOT ZERO jump to 05E1H; loop to test if A gets sent over the ring before a VINT happens.
05EBHCDAA05CALL 05AAHCall WAIT_VINT
05EEHCD4307CALL 0743HCall WAIT_255
05F1HCD2006CALL 0620HCall SEND_BYTE_BEFORE_VINT
05F4HCDAA05CALL 05AAHCall WAIT_VINT
05F7HCD4307CALL 0743HCall WAIT_255
05FAH3E01LD A,01HA = 0x01
05FCH320980LD (8009H),AMEM(0x0009) = A
05FFH3202C0LD (0C002H),ASHARE(0x0002) = A
0602HCD2006CALL 0620HCall SEND_BYTE_BEFORE_VINT; this gets called with A = 0x01, result value may be larger
0605H320880LD (8008H),AMEM(0x0008) = A
0608H3203C0LD (0C003H),ASHARE(0x0003) = A
060BHCDAA05CALL 05AAHCall WAIT_VINT
060EHCD4307CALL 0743HCall WAIT_255
0611H3A0880LD A,(8008H)A = MEM(0x0008)
0614HCD2006CALL 0620HCall SEND_BYTE_BEFORE_VINT
0617HCDFA06CALL 06FAHCall FLUSH_RXTX
061AHCD1B07CALL 071BHCall DISABLE_RXTX
061DHC3AC06JP 06ACHJump to VALIDATE_RING_SIZE
0620H - SEND_BYTE_BEFORE_VINT
# Binary ASM Comment
0620H320B80LD (800BH),AMEM(0x000B) = A
0623HCDAA05CALL 05AAHCall WAIT_VINT
0626HCD3107CALL 0731HCall FLUSH_RX
0629H21A800LD HL,00A8HHL = 0x00A8
062CH060ALD B,0AHB = 0x0A
062EHCDF409CALL 09F4HCall SETUP_REGISTERS_HL_B
0631H218000LD HL,0080HHL = 0x0080
0634H060ALD B,0AHB = 0x0A
0636HCDF409CALL 09F4HCall SETUP_REGISTERS_HL_B
0639HCD2807CALL 0728HCall ENABLE_RXTX
063CH3E3FLD A,3FHA = 0x3F
063EHD317OUT (17H),Awrite A to DLC 'Mask'; this may trigger a DMA transfer
0640HDB28IN A,(28H)read DMA 'Status Register'; 0x88, 0x80, ... 0xC4
0642HE604AND 04HA &= 4
0644HC25306JP NZ,0653HIf NON ZERO jump to 0653H
0647H3A0080LD A,(8000H)A = MEM(0x0000)
064AHB7OR AA |= A
064BHF24006JP P,0640HIf ?? jump to Call 0640H
064EH3EFFLD A,0FFHA = 0xFF
0650H320B80LD (800BH),AMEM(0x000B) = A
0653HCD3107CALL 0731HCall FLUSH_RX
0656H3A0C80LD A,(800CH)A = MEM(0x000C)
0659HC9RETreturn
065AH - SETUP_RING_SLAVE_RELAY
# Binary ASM Comment
065AHDB08IN A,(08H)read DLC 'Receive status 0'
065CH211E01LD HL,011EHHL = 0x011E
065FH0610LD B,10HB = 0x10
0661HCDF409CALL 09F4HCall SETUP_REGISTERS_HL_B
0664HCDBA06CALL 06BAHCall TRANSFER_SINGLE_BYTE_0
0667HFE4BCP 4BHx = A - 4BH
0669HC26406JP NZ,0664HIf NOT ZERO jump to 0664H
066CHCDBA06CALL 06BAHCall TRANSFER_SINGLE_BYTE_0
066FHFE61CP 61Hx = A - 61H
0671HC26C06JP NZ,066CHIf NOT ZERO jump to 066CH
0674HCDBA06CALL 06BAHCall TRANSFER_SINGLE_BYTE_0
0677HFE7ACP 7AHx = A - 7AH
0679HC27406JP NZ,0674HIf NOT ZERO jump to 0674H
067CHCDBA06CALL 06BAHCall TRANSFER_SINGLE_BYTE_0
067FH3A0680LD A,(8006H)A = MEM(0x0006)
0682H57LD D,AD = A; 0x01 on slave, 0x00 on relay
0683HCDBC06CALL 06BCHCall TRANSFER_SINGLE_BYTE_D
0686H320980LD (8009H),AMEM(0x0009) = A
0689HCDBA06CALL 06BAHCall TRANSFER_SINGLE_BYTE_0
068CH320880LD (8008H),AMEM(0x0008) = A
068FH3203C0LD (0C003H),ASHARE(0x0003) = A
0692HCDFA06CALL 06FAHCall FLUSH_RXTX
0695HCD1B07CALL 071BHCall DISABLE_RXTX
0698H3A0980LD A,(8009H)A = MEM(0x0009)
069BHFE01CP 01Hx = A - 0x01
069DH2807JR Z,06A6H ; (+07h)If ZERO jump to 06A6H
069FH47LD B,AB = A
06A0H3A0880LD A,(8008H)A = MEM(0x0008)
06A3HC602ADD A,02HA += 0x02
06A5H90SUB Bx = A - B
06A6H320980LD (8009H),AMEM(0x0009) = A
06A9H3202C0LD (0C002H),ASHARE(0x0002) = A
continued in VALIDATE_RING_SIZE
06ACH - VALIDATE_RING_SIZE
# Binary ASM Comment
void validateRingSize(){
	byte A;

	A = memr(0x8008);
	if (A < 9){
		return;
	} else {
		memw(0xC000, A);
		disableInterrupts();
		System.exit(A);
	}
}
06ACH3A0880LD A,(8008H)A = MEM(0x0008)
06AFHFE09CP 09Hx = A - 0x09
06B1HDAB906JP C,06B9HIf LESS jump to 06B9H
06B4H3200C0LD (0C000H),ASHARE(0x0000) = A
06B7HF3DIdisable interrupts
06B8H76HALThalt cpu
06B9HC9RETreturn
06BAH - TRANSFER_SINGLE_BYTE_0
06BCH - TRANSFER_SINGLE_BYTE_D
# Binary ASM Comment
06BAH1600LD D,00HD = 0
06BCHCD3107CALL 0731HCall FLUSH_RX
06BFH219400LD HL,0094HHL = 0x0094
06C2H060ALD B,0AHB = 0x0A
06C4HCDF409CALL 09F4HCall SETUP_REGISTERS_HL_B
06C7H218000LD HL,0080HHL = 0x0080
06CAH060ALD B,0AHB = 0x0A
06CCHCDF409CALL 09F4HCall SETUP_REGISTERS_HL_B
06CFH3E80LD A,80HA = 0x80
06D1HD30AOUT (0AH),Awrite A to DLC 'Receive control'
06D3H3EBFLD A,0BFHA = 0x0B
06D5HD317OUT (17H),Awrite A to DLC 'Mask'
06D7HDB28IN A,(28H)read DMA 'Status Register' to A
06D9HE604AND 04HA &= 0x04
06DBHCAD706JP Z,06D7HIf ZERO jump to 06D7H
06DEH3A0B80LD A,(800BH)A = MEM(0x000B)
06E1H82ADD A,DA += D
06E2H57LD D,AD = A
06E3H320B80LD (800BH),AMEM(0x000B) = A
06E6H3E80LD A,80HA = 0x80
06E8HD30DOUT (0DH),Awrite A to DLC 'Transmit control'
06EAH3E7FLD A,7FHA = 0x7F
06ECHD317OUT (17H),Awrite A to DLC 'Mask'
06EEHDB28IN A,(28H)read DMA 'Status Register' to A
06F0HE608AND 08HA &= 0x08
06F2HCAEE06JP Z,06EEHIf ZERO jump to 06EEH
06F5HCD3107CALL 0731HCall FLUSH_RX
06F8H7ALD A,DA = D
06F9HC9RETreturn
06FAH - FLUSH_RXTX
# Binary ASM Comment
06FAHDB0CIN A,(0CH)read DLC 'Transmit status' to A
06FCHE604AND 04HA &= 0x04
06FEHCAFA06JP Z,06FAHIf ZERO jump to 06FAH
0701HDB09IN A,(09H)read DLC 'Receive status 1' to A
0703HDB08IN A,(08H)read DLC 'Receive status 0' to A
0705HE601AND 01HA &= 0x01
0707HCA0F07JP Z,070FHIf ZERO jump to 070FH
070AHDB0FIN A,(0FH)read DLC 'Serial data' to A
070CHC30107JP 0701HJump to 0701H
070FHDB0CIN A,(0CH)read DLC 'Transmit status' to A
0711HAFXOR AA ^= A (=0)
0712HD30COUT (0CH),Awrite A to DLC 'Transmit status'
0714H3EFFLD A,0FFHA = 0xFF
0716HD317OUT (17H),Awrite A to DLC 'Mask'
0718HDB28IN A,(28H)read DMA 'Status Register' to A
071AHC9RETreturn
071BH - DISABLE_RXTX
# Binary ASM Comment
void disableRXTX(){
	iow(0x17, 0xFF);
	iow(0x0A, 0x03);
	iow(0x0D, 0x08);
}
071BH3EFFLD A,0FFHA = 0xFF
071DHD317OUT (17H),Awrite A to DLC 'Mask'
071FH3E03LD A,03HA = 0x03
0721HD30AOUT (0AH),Awrite A to DLC 'Receive control'
0723H3E08LD A,08HA = 0x08
0725HD30DOUT (0DH),Awrite A to DLC 'Transmit control'
0727HC9RETreturn
0728H - ENABLE_RXTX
# Binary ASM Comment
void enableRXTX(){
	iow(0x0A, 0x80);
	iow(0x0D, 0x80);
}
0728H3E80LD A,80HA = 0x80
072AHD30AOUT (0AH),Awrite A to DLC 'Receive control'
072CH3E80LD A,80HA = 0x80
072EHD30DOUT (0DH),Awrite A to DLC 'Transmit control'
0730HC9RETreturn
0731H - FLUSH_RX
# Binary ASM Comment
void flushRX(){
	byte A;

	flushRXTX();

	do {
		ior(0x09);
		A = ior(0x08);
		A &= 0x01;
		if (A == 0) {
			break;
		}
		A = ior(0x0F);
	}
}
0731HCDFA06CALL 06FAHCall FLUSH_RXTX
0734HDB09IN A,(09H)read DLC 'Receive status 1' to A
0736HDB08IN A,(08H)read DLC 'Receive status 0' to A
0738HE601AND 01HA &= 0x01
073AHCA4207JP Z,0742HIf ZERO jump to 0742H
073DHDB0FIN A,(0FH)read DLC 'Serial data'
073FHC33407JP 0734HJump to 0734H
0742HC9RETreturn
0731H - WAIT_255
# Binary ASM Comment
void wait255(){
	byte a = 0; ' a ^= a
	do (){
		a--;
	} while (a > 0);
}
0743HAFXOR AA ^= A
0744H3DDEC AA--
0745HC24407JP NZ,0744HIf NON ZERO jump to 0744H
0748HC9RETreturn
0749H - WAIT_20 (unused?)
# Binary ASM Comment
void wait20(){
	byte a = 0x14;
	do (){
		a--;
	} while (a > 0);
}
0749H3E14LD A,14H
074BH3DDEC A
074CHC24B07JP NZ,074BH
074FHC9RET
0750H - WAIT_40 (unused?)
# Binary ASM Comment
void wait40(){
	byte a = 0x28;
	do (){
		a--;
	} while (a > 0);
}
0750H3E28LD A,28H
0752H3DDEC A
0753HC25207JP NZ,0752H
0756HC9RET
0757H - LOOP_MASTER
# Binary ASM Comment
0757H3E00LD A,00H
0759H3200C0LD (0C000H),A; Status = 0
075CHCDBA07CALL 07BAHCall SYNC_COMMON
075FHCD4307CALL 0743HCall WAIT_255
0762HCDB409CALL 09B4HCall COPY_SHARE_TO_INT
0765H3E01LD A,01H
0767H3200C0LD (0C000H),A; Status = 1
076AH21A080LD HL,80A0H
076DH060ALD B,0AH
076FHCDF409CALL 09F4HCall SETUP_REGISTERS_HL_B
0772H21C080LD HL,80C0H
0775H060ALD B,0AH
0777HCDF409CALL 09F4HCall SETUP_REGISTERS_HL_B
077AHCDA007CALL 07A0HCall TRANSFER_DATA
077DHCDBA07CALL 07BAHCall SYNC_COMMON
0780H3A1380LD A,(8013H)A = MEM(0x0013)
0783HB7OR AA |= A
0784HCA9A07JP Z,079AHIf ZERO jump to 079AH
0787H21E080LD HL,80E0H
078AH060ALD B,0AH
078CHCDF409CALL 09F4HCall SETUP_REGISTERS_HL_B
078FH210081LD HL,8100H
0792H060ALD B,0AH
0794HCDF409CALL 09F4HCall SETUP_REGISTERS_HL_B
0797HCDA007CALL 07A0HCall TRANSFER_DATA
079AHCDCB09CALL 09CBHCall COPY_INT_TO_SHARE
079DHC35707JP 0757HJump to LOOP_MASTER
07A0H - TRANSFER_DATA
# Binary ASM Comment
07A0HCD2807CALL 0728HCall ENABLE_RXTX
07A3H3EBFLD A,0BFH
07A5HD317OUT (17H),Awrite 0xBF to DLC 'Mask'
07A7HCD4307CALL 0743HCall WAIT_255
07AAHCD4307CALL 0743HCall WAIT_255
07ADH3E3FLD A,3FH
07AFHD317OUT (17H),Awrite 0x3F to DLC 'Mask'; this starts transmitting
07B1H0604LD B,04H
07B3HCD5409CALL 0954HCall 0954H
07B6HCDFA06CALL 06FAHCall FLUSH_RXTX
07B9HC9RETreturn
07BAH - SYNC_COMMON
# Binary ASM Comment
07BAHCDFA06CALL 06FAHCall FLUSH_RXTX
07BDH21A800LD HL,00A8HHL = 0x00A8
07C0H060ALD B,0AHB = 0x0A
07C2HCDF409CALL 09F4HCall SETUP_REGISTERS_HL_B
07C5H218000LD HL,0080HHL = 0x0080
07C8H060ALD B,0AHB = 0x0A
07CAHCDF409CALL 09F4HCall SETUP_REGISTERS_HL_B
07CDHDB08IN A,(08H)read DLC 'Receive status 0' to A
07CFHCD2807CALL 0728HCall ENABLE_RXTX
07D2H3E33LD A,33HA = 0x33
07D4H320C80LD (800CH),AMEM(0x000C) = A
07D7H3EBFLD A,0BFHA = 0xBF
07D9HD317OUT (17H),Awrite A to DLC 'Mask'
07DBH210080LD HL,8000HHL = 0x8000
07DEHAFXOR AA ^= A (=0)
07DFH77LD (HL),A*HL* = A
07E0HBECP (HL)x = A - *HL*
07E1HCAE007JP Z,07E0HIf ZERO jump to 07E0H
07E4H3A04C0LD A,(0C004H)A = SHARE(0x0004)
07E7H320B80LD (800BH),AMEM(0x000B) = A
07EAH3E3FLD A,3FHA = 0x3F
07ECHD317OUT (17H),Awrite A to DLC 'Mask'
07EEHAFXOR AA ^= A (=0)
07EFH320080LD (8000H),AMEM(0x0000) = A
07F2H320580LD (8005H),AMEM(0x0005) = A
07F5H210C80LD HL,800CHHL = 0x800C
07F8H3A0080LD A,(8000H)A = MEM(0x0000)
07FBHB7OR AA |= A
07FCHCA0F08JP Z,080FHIf ZERO jump to 080FH
07FFH3A0580LD A,(8005H)
0802H3CINC A
0803HFE06CP 06H
0805HD27A09JP NC,097AH
0808H320580LD (8005H),A
080BHAFXOR A
080CH320080LD (8000H),A
080FH7ELD A,(HL)A = *HL*
0810HFE33CP 33Hx = A - 0x33
0812HCAF807JP Z,07F8HIf ZERO jump to 07F8H
0815HCDFA06CALL 06FAHCall FLUSH_RXTX
0818HDB28IN A,(28H)read DMA 'Status Register' to A
081AHCD4307CALL 0743HCall WAIT_255
081DH21D000LD HL,00D0H
0820H060ALD B,0AH
0822HCDF409CALL 09F4HCall SETUP_REGISTERS_HL_B
0825H21BC00LD HL,00BCH
0828H060ALD B,0AH
082AHCDF409CALL 09F4HCall SETUP_REGISTERS_HL_B
082DHDB08IN A,(08H)read DLC 'Receive status 0'
082FHCD2807CALL 0728HCall ENABLE_RXTX
0832H3E3FLD A,3FH
0834HD317OUT (17H),Awrite to DLC 'Mask'
0836H0604LD B,04H
0838HCD5409CALL 0954HCall 0954H
083BHCDFA06CALL 06FAHCall FLUSH_RXTX
083EHDB28IN A,(28H)read DLC 'Receive status 0'
0840HC9RETreturn
0841H - LOOP_SLAVE_RELAY
# Binary ASM Comment
0841H3E00LD A,00H
0843H3200C0LD (0C000H),A; Status = 0
0846HCDCB08CALL 08CBHCall READ_COMMON
0849H3A0780LD A,(8007H)A = MEM(0x0007)
084CHB7OR A
084DH2003JR NZ,0852H ; (+03h)If NON ZERO jump to 0852H
084FHCDB409CALL 09B4HCall COPY_SHARE_TO_INT
0852H3E01LD A,01H
0854H3200C0LD (0C000H),A; Status = 1
0857H21A080LD HL,80A0H
085AH060ALD B,0AH
085CHCDF409CALL 09F4HCall SETUP_REGISTERS_HL_B
085FH21C080LD HL,80C0H
0862H060ALD B,0AH
0864HCDF409CALL 09F4HCall SETUP_REGISTERS_HL_B
0867H2A0F80LD HL,(800FH)
086AHCD9308CALL 0893HCall 0893H
086DHCDCB08CALL 08CBHCall READ_COMMON
0870H3A1380LD A,(8013H)
0873HB7OR A
0874HCA8D08JP Z,088DHIf ZERO jump to 088DH
0877H21E080LD HL,80E0H
087AH060ALD B,0AH
087CHCDF409CALL 09F4HCall SETUP_REGISTERS_HL_B
087FH210081LD HL,8100H
0882H060ALD B,0AH
0884HCDF409CALL 09F4HCall SETUP_REGISTERS_HL_B
0887H2A1180LD HL,(8011H)
088AHCD9308CALL 0893HCall 0893H
088DHCDCB09CALL 09CBHCall COPY_INT_TO_SHARE
0890HC34108JP 0841HJump to LOOP_SLAVE_RELAY
0893H -
# Binary ASM Comment
0893HCD2807CALL 0728HCall ENABLE_RXTX
0896H3EDBLD A,0DBH
0898H77LD (HL),A
0899H47LD B,A
089AH3EBFLD A,0BFH
089CHD317OUT (17H),A
089EHAFXOR A
089FH3205C0LD (0C005H),A
08A2H320580LD (8005H),A
08A5H3A05C0LD A,(0C005H)
08A8HB7OR A
08A9HCABC08JP Z,08BCH
08ACH3A0580LD A,(8005H)
08AFH3CINC A
08B0HFE06CP 06H
08B2HD27A09JP NC,097AH
08B5H320580LD (8005H),A
08B8HAFXOR A
08B9H3205C0LD (0C005H),A
08BCH78LD A,B
08BDHBECP (HL)
08BEHCAA508JP Z,08A5H
08C1H3E3FLD A,3FH
08C3HD317OUT (17H),A
08C5H0608LD B,08H
08C7HCD5409CALL 0954HCall 0954H
08CAHC9RET
08CBH - READ_COMMON
# Binary ASM Comment
08CBHCDFA06CALL 06FAHCall FLUSH_RXTX
08CEH219400LD HL,0094H
08D1H060ALD B,0AH
08D3HCDF409CALL 09F4HCall SETUP_REGISTERS_HL_B
08D6H218000LD HL,0080H
08D9H060ALD B,0AH
08DBHCDF409CALL 09F4HCall SETUP_REGISTERS_HL_B
08DEHDB08IN A,(08H)
08E0HCD2807CALL 0728HCall ENABLE_RXTX
08E3H210B80LD HL,800BH
08E6H3EBFLD A,0BFH
08E8H3633LD (HL),33H
08EAHD317OUT (17H),A
08ECHAFXOR AA ^= A (=0)
08EDH3205C0LD (0C005H),A
08F0H320580LD (8005H),A
08F3H3A05C0LD A,(0C005H)
08F6HB7OR A
08F7HCA0A09JP Z,090AHIf ZERO jump to 090AH
08FAH3A0580LD A,(8005H)
08FDH3CINC A
08FEHFE06CP 06H
0900HD27A09JP NC,097AH
0903H320580LD (8005H),A
0906HAFXOR A
0907H3205C0LD (0C005H),A
090AH7ELD A,(HL)A = MEM(0x000B)
090BHFE33CP 33Hx = A - 33
090DHCAF308JP Z,08F3HIf ZERO jump to 08F3H
0910H3E3FLD A,3FH
0912HD317OUT (17H),A
0914H3E01LD A,01H
0916HD340OUT (40H),Awrite 0x01 to SYN; enables DOP
0918HAFXOR A
0919HD340OUT (40H),Awrite 0x00 to SYN; disables DOP
091BHDB28IN A,(28H)read DMA 'Status Register'
091DHE608AND 08Hx = A &= 0x08
091FHCA1B09JP Z,091BHIf ZERO jump to 091BH
0922HCDFA06CALL 06FAHCall FLUSH_RXTX
0925HDB28IN A,(28H)
0927H21D000LD HL,00D0H
092AH060ALD B,0AH
092CHCDF409CALL 09F4HCall SETUP_REGISTERS_HL_B
092FH21BC00LD HL,00BCH
0932H060ALD B,0AH
0934HCDF409CALL 09F4HCall SETUP_REGISTERS_HL_B
0937HDB08IN A,(08H)
0939HCD2807CALL 0728HCall ENABLE_RXTX
093CH3EBFLD A,0BFH
093EHD317OUT (17H),A
0940H0604LD B,04H
0942HCD5409CALL 0954HCall 0954H
0945H3E3FLD A,3FH
0947HD317OUT (17H),A
0949H0608LD B,08H
094BHCD5409CALL 0954HCall 0954H
094EHCDFA06CALL 06FAHCall FLUSH_RXTX
0951HDB28IN A,(28H)
0953HC9RET
0954H -
# Binary ASM Comment
0954HAFXOR AA = 0
0955H320580LD (8005H),AMEM(0x0005) = A
0958H3205C0LD (0C005H),ASHARE(0x0005) = A
095BH3A05C0LD A,(0C005H)A = SHARE(0x0005)
095EHB7OR AA |= A
095FHCA7209JP Z,0972HIf ZERO jump to 0972H
0962H3A0580LD A,(8005H)
0965H3CINC A
0966HFE06CP 06H
0968HD27A09JP NC,097AH
096BH320580LD (8005H),A
096EHAFXOR A
096FH3205C0LD (0C005H),A
0972HDB28IN A,(28H)read DMA 'Status Register' to A
0974HA0AND Bx = A &= B
0975HB8CP Bx = A - B
0976HC25B09JP NZ,095BHIf NON ZERO jump to 095BH
0979HC9RETreturn
0954H -
# Binary ASM Comment
097AHAFXOR A
097BH320A80LD (800AH),Awrite 0x00 to MEM(0x000A)
097EH21F800LD HL,00F8H
0981H114080LD DE,8040H
0984H012600LD BC,0026H
0987HEDB0LDIRcopy 0x0026 bytes from 0x00F8 to 0x8040
0989H3E08LD A,08H
098BH3200C0LD (0C000H),A
098EH320E80LD (800EH),A
0991H3E01LD A,01H
0993H3203C0LD (0C003H),A
0996H3202C0LD (0C002H),A
0999H320980LD (8009H),A
099CH3E02LD A,02H
099EHD340OUT (40H),Awrite 0x02 to SYN (enable VINT)
09A0HFBEIenable interrupts
09A1HCDAF05CALL 05AFHCall 05AFH
09A4H3A04C0LD A,(0C004H)
09A7HB7OR A
09A8HCAA109JP Z,09A1HIf ZERO jump to 09A1H
09ABHCDD009CALL 09D0HCall COPY_INT_TO_SHARE_X
09AEHCDB909CALL 09B9HCall COPY_SHARE_TO_INT_X
09B1HC3A109JP 09A1HJump to 09A1H
09B4H - COPY_SHARE_TO_INT
09B9H - COPY_SHARE_TO_INT_X
# Binary ASM Comment
09B4H3E03LD A,03H
09B6H3200C0LD (0C000H),A
09B9H21F800LD HL,00F8H
09BCHCDF209CALL 09F2HCall SETUP_REGISTERS_HL_13
09BFH0603LD B,03H
09C1HCDFC09CALL 09FCHCall WAIT_DMA_STATUS_B
09C4H3A0E80LD A,(800EH)
09C7H3200C0LD (0C000H),A
09CAHC9RET
09CBH - COPY_INT_TO_SHARE
09D0H - COPY_INT_TO_SHARE_X
# Binary ASM Comment
09CBH3E02LD A,02H
09CDH3200C0LD (0C000H),ASHARE(0x0000) = 0x02
09D0H3EFFLD A,0FFH
09D2HD32FOUT (2FH),Awrite 0xFF to DMA 'MultiChannel Mask Register'
09D4HCDEF09CALL 09EFHCall SETUP_REGISTERS_8040_13
09D7H0603LD B,03H
09D9HCDFC09CALL 09FCHCall WAIT_DMA_STATUS_B
09DCH3A0A80LD A,(800AH)A = MEM(0x000A)
09DFHB7OR AA |= A
09E0HCAEE09JP Z,09EEHIf ZERO jump to 09EEH
09E3H217080LD HL,8070H
09E6HCDF209CALL 09F2HCall SETUP_REGISTERS_HL_13
09E9H0603LD B,03H
09EBHCDFC09CALL 09FCHCall WAIT_DMA_STATUS_B
09EEHC9RETreturn
09EFH - SETUP_REGISTERS_8040_13
09F2H - SETUP_REGISTERS_HL_13
09F4H - SETUP_REGISTERS_HL_B
# Binary ASM Comment
void setupRegisters_HLB(){
	setupRegisters_HLB(0x8040);
}

void setupRegisters_HLB(int HL){
	setupRegisters_HLB(HL, 0x13);
}

void setupRegisters_HLB(int HL, int B){
	do {
		byte C = memr(HL);
		HL++;
		iow(C, memr(HL));
		B--;
	} while (B > 0);
}
09EFH214080LD HL,8040HHL = 0x8040
09F2H0613LD B,13HB = 19
09F4H4ELD C,(HL)C = *HL*
09F5H23INC HLHL++
09F6HEDA3OUTIread from HL, write to C, decrease B
09F8HC2F409JP NZ,09F4Hwhile B > 0 jump to SETUP_REGISTERS_HL_B
09FBHC9RETreturn
09EFH - WAIT_DMA_STATUS_B (read while status matches anything in B)
# Binary ASM Comment
09FCHDB28IN A,(28H)read DMA 'Status Register'
09FEHA0AND Bx = A &= B
09FFHB8CP Bx = x - B
0A00HC2FC09JP NZ,09FCHIf NON ZERO jump to 09FCH
0A03HC9RETreturn
0A04HFFRST 38H